SA24C1024 Datasheet, PDF (15/27 Pages) List of Unclassifed Manufacturers – 1024Kb EEPROM IIC

SA24C1024 Datasheet
SAIFUN
15
Choice 2: Programmable Write Protect ⁽¹⁾
The Programmable Write protection is available to customers by contacting a Sales
Representative. For this option, use an internal 8-bit wide internal NV-Latch with the following
definition:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A16 A15 A14 A13 A12 A11 A10 T/B
Top or Bottom Selection - Bit[0]
0 = Protects from address 0x0000 up to the
address set in Bits[7:1].
1 = Protects from address 1xFFFF up to the
address set in Bits[7:1].
Address Protection Range - Bit[7:1]
These 7 MSBs of array address determine the
address range that needs to be protected.
1 _{Predefined on Sort. Not a user command.}
Example
(1024K )
1
2
3
4
5
6
Write Protection
Area
Full Array
(0x0000 – 0x1FFFF)
Bottom Half
(0x0000 – 0x0FFFF)
Bottom Quadrant
(0x0000 – 0x07FFF)
Top Quadrant
(0x18000 – 0x1FFFF)
Top Half
(0x10000 – 0x1FFFF)
No Write Protection
NV-Latch Bit
Setting - Bits [7:0]
Result
0-0-0-0-0-0-0-1
Address bits (A16:A10) issued during the Write
command are compared against bits[7:1] of this
NV-Latch. As bit[0] of this NV-Latch is set to 1, Write
is not allowed as long as the comparison results in a
greater than or equal to status.
1-0-0-0-0-0-0-0 As in example 1.
0-1-0-0-0-0-0-0
1-1-0-0-0-0-0-1
1-0-0-0-0-0-0-1
0-0-0-0-0-0-0-0
As in example 1.
Address bits (A16:A10) issued during the Write
command are compared against bits[7:1] of this
NV-Latch. As bit[0] of this NV-Latch is set to 1, Write
is allowed as long as the comparison results in a
greater than or equal to status.
As in example 4.
As in example 4.