SI5022 Datasheet, PDF (14/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP

Si5022/Si5023
test signal that is degraded with sinusoidal jitter whose used to reduce power consumption in applications that
magnitude is defined by the mask in Figure 9.
do not use the recovered clock.
Jitter
Transfer
0.1 dB
Acceptable
Range
20 dB/Decade
Slope
Data Squelch
The Si5022/23 provides a data squelching pin,
DSQLCH, that is used to set the recovered data output,
DOUT, to binary zero. When the DSQLCH pin is
asserted, the DOUT logic signal is held at a binary zero.
This pin can be is used to squelch corrupt data during
LOS and LOL situations. Care must be taken when ac
coupling these outputs; a long string of zeros will not be
held through ac coupling capacitors.
Device Grounding
Fc
Frequency
SONET
Data Rate
OC-48
OC-12
OC-3
Fc
(kHz)
2000
500
130
Figure 9. Jitter Transfer Specification
Jitter Generation
The Si5022/23 exceeds all relevant specifications for
jitter generation proposed for SONET/SDH equipment.
The jitter generation specification defines the amount of
jitter that may be present on the recovered clock and
data outputs when a jitter free input signal is provided.
The Si5022/23 typically generates less than
3.0 mUI_RMS of jitter when presented with jitter-free input
data.
RESET/DSPLL Calibration
The Si5022/23 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed TBD V when calibration occurs. Self-
calibration is initiated by a high-to-low transition on the
RESET/CAL pin. The RESET/CAL pin must be held
high for at least 1 µS after the supply has stabilized on
power-up for optimum device operation. When RESET/
CAL is released (set to low) the digital logic resets to a
known initial condition, recalibrates the DSPLL, and will
begin to lock to the incoming data stream.
Clock Disable
The Si5022/23 provides a clock disable pin,
CLK_DSBL, that is used to disable the recovered clock
output, CLKOUT. When the CLK_DSBL pin is asserted,
the positive and negative terminals of CLKOUT are tied
to VDD through 100 Ω on-chip resistors. This feature is
The Si5022/23 uses the GND pad on the bottom of the
28-pin micro leaded package (MLP) for device ground.
This pad should be connected directly to the analog
supply ground. See Figures 13 and 14 for the ground
(GND) pad location.
Bias Generation Circuitry
The Si5022/23 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
Voltage Regulator
The Si5022 and Si5023 operate from different external
supply voltages. Internally the devices are identical and
operate from a 2.5 V supply. The Si5022 takes the 2.5 V
supply directly from the external supply connections.
The Si5023 regulates 2.5 V internally down from the
external 3.3 V supply. Both devices consume 148 mA
typically.
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus the direct 2.5 V supply.
Differential Input Circuitry
The Si5022/23 provides differential inputs for both the
high speed data (DIN) and the reference clock
(REFCLK) inputs. An example termination for these
inputs is shown in Figure 10 and Figure 11 respectively.
In applications where direct dc coupling is possible, the
0.1 µF capacitors may be omitted. (LOS operation is
only guaranteed when ac coupled.) The data input
limiting amplifier requires an input signal with a
differential peak-to-peak voltage as specified in Table 2
to ensure a BER of at least 10^–12. The REFCLK input
differential peak-to-peak voltage requirement is
specified in Table 2.
14
Preliminary Rev. 0.46