SI5022 Datasheet, PDF (13/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP

Si5022/Si5023
Approximately 6 dB of level detection hysteresis
prevents unnecessary switching on LOS when marginal
input data swing peak-to-peak levels are present.
Hysteresis is defined as the difference between the LOS
deassert level (LOSD) and the LOS assert level
(LOSA). The hysteresis in decibels is calculated as
20log((LOSD – LOSA)/LOSA). The relationship
between the LOS assert level and the LOS deassert
level is shown in Figure 7. When the LOS assert level is
set below 10 mV, the amount of hysteresis is fixed at
5 mV. When the LOS assert level is set above 10 mV,
the amount of hysteresis is approximately 6 dB.
common mode voltage) are supported. The 0/1 slicing
level is set by applying a voltage between 0.75 V and
2.25 V to the SLICE_LVL input. The voltage present on
SLICE_LVL maps to the 0/1 slicing level as follows:
V_SLICE
=
(_---V_{----S----L---I-C----E----_--L---V---L----–----}1_----._-5_------V_-----)
50
where V_SLICE is the slicing level and V_{SLICE_LVL} is the
voltage applied to the SLICE_LVL pin.
When SLICE_LVL is driven below 500 mV, the 0/1
slicing level adjustment is disabled, and the slicing level
is set to the cross-point of the differential input signal.
45 mV
15 mV
11 mV
PLL Performance
The PLL implementation used in the Si5022/23 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5022/23’s tolerance to input jitter exceeds that of
the Bellcore/ITU mask shown in Figure 8. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note: There are no entries in the mask table for the data rate
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
LOS Assert Level (mV_PP)
Figure 7. Hysteresis Dependency
Sinusoidal
Input
Jitter (UI_PP)
15
1.5
Slope = 20 dB/Decade
Bit-Error-Rate (BER) Detection
0.15
The Si5022/23 uses a proprietary Silicon Laboratories
algorithm to generate a bit-error-rate (BER) alarm on
the BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
of the expected event window are counted as bit errors.
The BER alarm threshold can be set to one of 64
discrete values between 10^–3 and 10^–4. The BER
threshold is programmed by applying a voltage to the
BER_LVL pin between 500 mV and 2.25 V
corresponding to 10^-3 and 10^-4 respectively.
Data Slicing Level
The Si5022/23 provides the ability to externally adjust
the 0/1 slicing level for applications that require bit-
error-rate (BER) optimization. Adjustments in slicing
level of ±15 mV (relative to the internally set input
f0
f1
f2
f3 ft
Frequency
SONET
Data Rate
OC-48
OC-12
OC-3
F0
(Hz)
10
10
10
F1
(Hz)
600
30
30
F2
(kHz)
6000
300
300
F3
(kHz)
100
25
6.5
Ft
(kHz)
1000
250
65
Figure 8. Jitter Tolerance Specification
Jitter Transfer
The Si5022/23 exceeds all relevant Bellcore/ITU
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency. (See
Figure 9.) These measurements are made with an input
Preliminary Rev. 0.46
13