SI5022 Datasheet, PDF (12/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP

Si5022/Si5023
Operation With an External Reference
The Si5022/23 device’s optional external reference
clock centers the DSPLL, minimizes the acquisition
time, and maintains a stable output clock (CLKOUT)
when lock-to-reference (LTR) is asserted.
When the reference clock is present, the Si5022/23 will
use the reference clock to center the VCO output
frequency so that clock and data can be recovered from
the input data stream. The device will self configure for
operation with one of three reference clock frequencies.
This eliminates the need to externally configure the
device to operate with a particular reference clock.
The reference clock centers the VCO for a nominal
output between 2.5 and 2.7 GHz. The VCO frequency is
centered at 16, 32, or 128 times the reference clock
frequency. Detection circuitry continuously monitors the
reference clock input to determine whether the device
should be configured for a reference clock that is 1/16,
1/32, or 1/128 the nominal VCO output. Approximate
reference clock frequencies for some target applications
are given in Table 8.
Table 8. Typical REFCLK Frequencies
SONET/SDH
Gigabit
Ethernet
SONET/
SDH with
15/14 FEC
19.44 MHz 19.53 MHz 20.83 MHz
77.76 MHz 78.125 MHz 83.31 MHz
155.52 MHz 156.25 MHz 166.63 MHz
Ratio of
VCO to
REFCLK
128
32
16
Lock Detect
The Si5022/23 provides lock-detect circuitry that
indicates whether the PLL has achieved frequency lock
with the incoming data. The operation of the lock-
detector depends on the reference clock option used.
When an external reference clock is provided, the circuit
compares the frequency of a divided down version of
the recovered clock with the frequency of the supplied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the DSPLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
will drift over a 1% range relative to the supplied
reference clock. The LOL output will remain asserted
until the recovered clock frequency is within the
REFCLK frequency by the amount specified in Table 4
on page 9. In applications requiring a more stable
output clock during out-of-lock conditions, the lock-to-
reference (LTR) input can be used to force the PLL to
lock to the externally supplied reference.
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. Once LOL has been asserted, it will remain
active until data is reacquired. During this reacquisition
period, CLKOUT may vary by approximately ±10% from
the nominal data rate. For applications requiring a more
stable output clock during out-of-lock conditions, LTR
can be used to stabilize the output clock.
Lock-to-Reference
The lock-to-reference input (LTR) can be used to force a
stable output clock when an alarm condition, like LOS,
exists. In typical applications, the LOS output would be
tied to the LTR input to force a stable output clock when
the input data signal is lost. When LTR is asserted, the
DSPLL is prevented from acquiring the data signal
present on DIN. The operation of the LTR control input
depends on which reference clocking mode is used.
When an external reference clock is present, assertion
of LTR will force the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR will force the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces an output clock that is stable as long as
supply and temperature are constant.
Loss-of-Signal
The Si5022/23 indicates a loss-of-signal condition on
the LOS output pin when the input peak-to-peak signal
level on DIN falls below an externally controlled
threshold. The LOS threshold range is specified in
Table 3 and is set by applying a voltage on the
LOS_LVL pin. The graph in Figure 6 illustrates the
LOS_LVL mapping to the LOS threshold. The LOS
output is asserted when the input signal drops below the
programmed peak-to-peak value.
30 mV
15 mV
40m V/V
0 mV
0V
1.00 V
1.50 V
1.875 V
2.25 V
LOS_LVL (V)
Figure 6. LOS_LVL Mapping
12
Preliminary Rev. 0.46