M13S2561616A-2A Datasheet, PDF (9/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S2561616A (2A)
Automotive Grade
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
Parameter
Clock period
CL2
CL2.5
CL3
CL4
DQ output access time from CLK/ CLK
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
Clock to first rising edge of DQS delay
DQ and DM input setup time (to DQS)
DQ and DM input hold time (to DQS)
DQ and DM input pulse width (for each
input)
Address and Control input setup time
(fast)
Address and Control input hold time
(fast)
Address and Control input setup time
(slow)
Address and Control input hold time
(slow)
Control and Address input pulse width
(for each input)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Data strobe edge to output data edge
Data-out high-impedance time from
CLK/ CLK
Data-out low-impedance time from
CLK/ CLK
Clock half period
Symbol
t_CK
t_AC
t_CH
t_CL
t_DQSCK
t_DQSS
t_DS
t_DH
t_DIPW
t_IS
t_IH
t_IS
t_IH
t_IPW
t_DQSH
t_DQSL
t_DSS
t_DSH
t_DQSQ
t_HZ
t_LZ
t_HP
-4
min
max
7.5
12
5
12
4
10
4
10
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.55 +0.55
0.72
1.25
0.4
0.4
1.75
0.6
0.6
0.8
0.8
2.2
0.35
0.35
0.2
0.2
0.4
+0.7
-0.7
t_CLmin
or
t_CHmin
+0.7
-5
min
max
7.5
12
5
12
5
12
-
-
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.72
1.25
0.4
0.4
1.75
0.6
0.6
0.8
0.8
2.2
0.35
0.35
0.2
0.2
0.4
+0.7
-0.7
t_CLmin
or
t_CHmin
+0.7
-6
min
max
7.5
12
6
12
6
12
-
-
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.72
1.25
0.4
0.4
1.75
0.6
0.6
0.8
0.8
2.2
0.35
0.35
0.2
0.2
0.4
+0.7
-0.7
t_CLmin
or
t_CHmin
+0.7
Unit Note
ns
ns
t_CK
t_CK
ns
t_CK
ns
ns
ns 18
ns
15,
17~19
ns
15,
17~19
ns 16~19
ns 16~19
ns 18
t_CK
t_CK
t_CK
t_CK
ns
22
ns
11
ns
11
ns 20,21
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.1
9/49