M13S2561616A-2A Datasheet, PDF (10/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S2561616A (2A)
Automotive Grade
AC Timing Parameter & Specifications – continued
Parameter
Symbol
-4
min
max
DQ/DQS output hold time from DQS
Data hold skew factor
Active to Precharge command
Active to Active / Auto Refresh
command period
t_QH
t_QHS
t_RAS
t_RC
t_HP- t_QHS
0.5
36
70K
52
Auto Refresh to Active / Auto Refresh
command period
t_RFC
60
Active to Read, Write delay
Precharge command period
Active to Read with Auto Precharge
command
t_RCD
15
t_RP
15
t_RAP
15
Active bank A to Active bank B
command
t_RRD
8
Write recovery time
t_WR
15
Write data in to Read command delay
t_WTR
2
Average periodic refresh interval for
T_A ≤ 85℃
t_REFI
7.8
Average periodic refresh interval for T_A
＞85℃ (VA grade only)
t_REFI
1.95
Write preamble
t_WPRE
0.25
Write postamble
t_WPST
0.4
0.6
Read preamble
t_RPRE
0.9
1.1
Read postamble
t_RPST
0.4
0.6
Clock to DQS write preamble setup time t_WPRES
0
Mode Register Set command cycle time t_MRD
2
Exit self refresh to Read command
t_XSRD
200
Exit self refresh to non-Read command
Auto Precharge write
recovery+precharge time
t_XSNR
t_DAL
75
(t_WR/t_CK)
+
(t_RP/t_CK)
-5
min
max
t_HP- t_QHS
0.5
40
70K
-6
min
max
t_HP- t_QHS
0.5
42
70K
55
60
70
72
15
18
15
18
15
18
10
12
15
15
2
2
7.8
7.8
1.95
1.95
0.25
0.25
0.4
0.6
0.4
0.6
0.9
1.1
0.9
1.1
0.4
0.6
0.4
0.6
0
0
2
2
200
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
75
(t_WR/t_CK)
+
(t_RP/t_CK)
Unit Note
ns 21
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
us
14
us 14
t_CK
t_CK
12
t_CK
t_CK
ns 13
t_CK
t_CK
ns
t_CK
23
Notes:
1.
2.
3.
All voltages referenced to V_SS.
Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.1
10/49