M13S2561616A-2A Datasheet, PDF(1/49 Page) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

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M13S2561616A-2A Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT

M13S2561616A (2A)

Automotive Grade

DDR SDRAM

4M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Features

z Double-data-rate architecture, two data transfers per clock cycle

z Bi-directional data strobe (DQS)

z Differential clock inputs (CLK and CLK )

z DLL aligns DQ and DQS transition with CLK transition

z Four bank operation

z CAS Latency : 2, 2.5, 3, 4

z Burst Type : Sequential and Interleave

z Burst Length : 2, 4, 8

z All inputs except data & DM are sampled at the rising edge of the system clock (CLK)

z Data I/O transitions on both edges of data strobe (DQS)

z DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

z Data mask (DM) for write masking only

z VDD = 2.5V Â± 0.2V, VDDQ = 2.5V Â± 0.2V

z 7.8us refresh interval for V grade; 1.95us refresh interval for VA grade

z Auto & Self refresh (self refresh is not supported for VA grade)

z 2.5V I/O (SSTL_2 compatible)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.1

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