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M13S128324A_1 Datasheet, PDF (9/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM | |||
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ESMT
M13S128324A
Operation Temperature Condition -40~85°C
Command Truth Table
COMMAND
A11~A9,
CKEn-1 CKEn CS RAS CAS
WE DM BA0,1
A8/AP
Note
A7~A0
Register
Extended MRS
H
XLL
L
LX
OP CODE
1,2
Register
Mode Register Set
H
XLL
L
LX
OP CODE
1,2
Auto Refresh
H
3
H
LL
L
HX
X
Entry
L
3
Refresh
Self
Refresh
Exit
LH
H
H
L
H
X
X
3
HX
X
X
3
Bank Active & Row Addr.
H
XLL
H
HX
V
Row Address
Read & Auto Precharge Disable
Column
H
Address Auto Precharge Enable
XLH
L
HX
V
L
4
Column
H
Address 4
Write & Auto Precharge Disable
Column
H
Address Auto Precharge Enable
XLH
L
LX
V
L
4
Column
H
Address 4,6
Burst Stop
H
XLH
H
LX
X
7
Precharge
Bank Selection
All Banks
V
L
H
XLL
H
LX
X
H
X
5
HX
X
X
Entry
H
L
X
Active Power Down
LV
V
V
X
Exit
L
HXX
X
XX
HX
X
X
Entry
H
L
X
Precharge Power Down
Mode
LH
H
H
X
HX
X
X
Exit
L
H
X
LV
V
V
DM
H
X
V
X
8
HX
X
X
No Operation Command
H
X
X
X
LH
H
H
(V = Valid, X = Donât Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by âAutoâ..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are âLowâ at read, write, row active and precharge, bank A is selected.
If BA0 is âHighâ and BA1 is âLowâ at read, write, row active and precharge, bank B is selected.
If BA0 is âLowâ and BA1 is âHighâ at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are âHighâ at read, write, row active and precharge, bank D is selected.
5. If A8/AP is âHighâ at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
9/49
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