|
M13S128324A_1 Datasheet, PDF (31/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM | |||
|
◁ |
ESMT
M13S128324A
Operation Temperature Condition -40~85°C
Current State CS RAS CAS WE
Address
Command
H X X XX
DESEL
L H H HX
NOP
L H H L BA
Burst Stop
L H L X BA, CA, A8
RE-FRESHING
L
L
H
H BA, RA
READ/WRITE
Active
L
L
H
L BA, A8
PRE / PREA
L
L
L
HX
Refresh
L
L
L
L Op-Code Mode-Add MRS
H X X XX
DESEL
L H H HX
NOP
L H H L BA
MODE
L H L X BA, CA, A8
REGISTER
SETTING
L
L
H
H BA, RA
Burst Stop
READ / WRITE
Active
L
L
H
L BA, A8
PRE / PREA
L
L
L
HX
Refresh
L
L
L
L Op-Code Mode-Add MRS
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Donât Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bankâs previous auto precharg will not be performed. But if the bank is different, previous auto precharge will
be performed.
7. Refer to âRead with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
31/49
|
▷ |