M13S128324A_1 Datasheet, PDF (6/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DC Specifications
M13S128324A
Operation Temperature Condition -40~85°C
Parameter
Symbol
Test Condition
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
Idle Standby Current
Active Power-down Standby
Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
IDD0
IDD1
t_RC = t_RC (min) t_CK = t_CK (min)
Active – Precharge
Burst Length = 2 t_RC = t_RC (min),
CL= 2.5 I_OUT = 0mA,
Active-Read- Precharge
IDD2P
CKE ≤ V_IL(max), t_CK = t_CK (min),
All banks idle
IDD2N ^{CKE ≥ VIH(min), CS ≥}
V_IH(min), t_CK = t_CK (min)
IDD3P
All banks ACT, CKE ≤ V_IL(max),
t_CK = t_CK (min)
One bank; Active-Precharge, t_RC
IDD3N = tRAS(max),
t_CK = t_CK (min)
IDD4R
Burst Length = 2, CL= 2.5 , t_CK =
t_CK (min), I_OUT = 0Ma
IDD4W
Burst Length = 2, CL= 2.5 , t_CK =
t_CK (min)
IDD5 t_RC ≥ t_RFC(min)
IDD6 CKE ≤ 0.2V
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
Version
-5
-6
175
145
190
180
40
40
115
95
50
45
120
110
350
300
380
330
270
250
3
3
Unit Note
-
-
mA
-
mA
-
mA
-
mA
-
mA
-
mA
-
mA
-
mA
-
mA
-
mA
1
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
Min
V_REF + 0.35
-
0.7
Max
-
V_REF - 0.35
V_DDQ+0.6
Unit
V
V
V
Note
-
-
1
Input Crossing Point Voltage, CLK and CLK inputs
V_IX(AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
2
Note1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of
the same.
Input / Output Capacitance
(V_DD = 2.375V~2.75V, V_DDQ =2.375V~2.75V, T_A = 25 °C , f = 1MHz)
Parameter
Symbol Min
Max
Unit
Input capacitance(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
C_IN1
1
4
pF
Input capacitance (CLK, CLK )
C_IN2
1
5
pF
Data & DQS input/output capacitance
Input capacitance (DM)
C_OUT
1
6.5
pF
C_IN3
1
6.5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
6/49