M13S128324A_1 Datasheet, PDF (33/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
Operation Temperature Condition -40~85°C
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
33/49