M13S64164A-2Y Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
IDD Specifications
Symbol
-4
IDD0
75
IDD1
85
IDD2P
IDD2F
40
IDD2Q
40
IDD3P
15
IDD3N
70
IDD4R
130
IDD4W
120
IDD5
70
IDD6
IDD7
150
Version
-5
65
75
8
35
35
15
60
120
110
60
3
130
M13S64164A (2Y)
Automotive Grade
Unit
-6
55
mA
65
mA
mA
30
mA
30
mA
15
mA
50
mA
110
mA
100
mA
50
mA
mA
110
mA
Input / Output Capacitance
Parameter
Package
Input capacitance (A0~A11, BA0~BA1,
CKE, CS , RAS , CAS , WE )
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
Symbol
C_IN1
C_IN2
C_OUT
C_IN3
Min
2
TBD
2
TBD
2
TBD
2
TBD
Max
4
TBD
4
TBD
6
TBD
4
TBD
Delta Cap
(max)
0.5
0.25
0.5
0.5
Unit Note
pF
1,4
pF
pF
1,4
pF
pF
1,2,3,4
pF
pF
1,2,3,4
pF
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. For all devices, V_DDQ = 2.5V ± 0.2V, V_DD = 2.5V ± 0.2V. f=100MHz, T_A =25°C, V_OUT(DC) =
V_DDQ/2, V_OUT (peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in
loading (to facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
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