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M13S2561616A_09 Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
◁
ESMT
M13S2561616A
AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE command
Row Cycle Time
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
ACTIVE to READ with AUTOPRECHARGE
command
Symbol
tHP
tQH
-4
min
tCLmin or
tCHmin
tHP-tQHS
max
-
-
tQHS
-
0.45
tRAS
40
70K
tRC
52
-
tRFC
64
-
tRCD
15
-
tRP
15
-
tRAP
18
120K
ACTIVE bank A to ACTIVE bank B
command
tRRD
8
-
Write recovery time
tWR
15
-
Write data in to READ command delay
tWTR
2
-
Col. Address to Col. Address delay
tCCD
1
-
Average periodic refresh interval
tREFI
-
7.8
Write preamble
tWPRE
0.25
-
Write postamble
tWPST
0.4
0.6
DQS read preamble
tRPRE
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
Clock to DQS write preamble setup time
tWPRES
0
-
Load Mode Register / Extended Mode
register cycle time
tMRD
2
-
Exit self refresh to READ command
tXSRD
200
-
Exit self refresh to non-READ command
tXSNR
75
-
Autoprecharge write recovery + Precharge
time
tDAL
30
-
-5
min
tCLmin or
tCHmin
tHP-tQHS
max
-
-
-
0.45
40
70K
55
-
70
-
15
-
15
-
18
120K
10
-
15
-
2
-
1
-
-
7.8
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
2
-
200
-
75
-
30
-
-6
min
tCLmin or
tCHmin
tHP-tQHS
max
-
-
-
0.5
42
70K
60
-
72
-
18
-
18
-
18
120K
12
-
15
-
1
-
1
-
-
7.8
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
1
-
200
-
75
-
-
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
us
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2009
Revision : 2.0
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