M13S2561616A_09 Datasheet, PDF (24/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S2561616A
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when t_RAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until t_RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (t_RP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
CL K
C LK
C OM M A ND
Ba nk A
A CTI VE
CA S Lat en cy=3
DQS
DQ's
NOP
t R AP
R ea d A
Auto Pre cha rg e
NOP
4
NOP
5
6
7
NOP
NOP
NOP
D o ut 0 Do u t 1 Do u t 2 Do u t 3
8
NOP
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping t_WR(min).
<Burst Length = 4>
0
1
2
CLK
CLK
COMMAND
Bank A
ACTIVE
NOP
Write A
Auto Precharge
3
NOP
4
NOP
5
6
NOP
NOP
7
NOP
8
NOP
DQS
DQ's
Dout 0 Dout 1 Dout 2 Dout 3
*Bank can be reactivated at
completion of tRP
tWR
In tern al p rech arge start
tRP
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2009
Revision : 2.0
24/49