M12L64164A_07 Datasheet, PDF (6/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
PARAMATER
CLK cycle time
CAS latency = 3
CAS latency = 2
CLK to valid
output delay
CAS latency = 3
CAS latency = 2
Output data
hold time
CAS latency = 3
CAS latency = 2
CLK high pulsh width
CLK low pulsh width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency = 3
CAS latency = 2
SYMBOL
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-5
MIN MAX
5
-
10
-
4.5
-
6
2.0
-
2.0
-
2.5
-
2.5
-
1.5
-
1
-
0
-
-
5.5
-
5.5
-6
MIN MAX
6
-
10
-
5.5
-
6
2.5
-
2.5
-
2.5
-
2.5
-
1.5
-
1
-
0
-
-
5.5
-
6
-7
MIN MAX
7
-
10
-
6
-
6
2.5
-
2.5
-
2.5
-
2.5
-
1.5
-
1
-
0
-
-
6
-
6
UNIT NOTE
ns
1
ns
1,2
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
-
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 3.0
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