M12L64164A_07 Datasheet, PDF (34/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Page Write Cycle at Different Bank @ Burst Length = 4
M12L64164A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
A13
A12
RBb CAa
CBb RCc
RDd CCc
CDd
*Note2
A10/AP
RAa
RBb
RCc
RDd
DQ
WE
DQM
DAa0 _{DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0} DCc1 _DDd0 DDd1 CDd2
tCDL
tRDL
*Note1
Row Active
( A - Bank )
Write
(A -Ba nk )
Row Active
( B-Bank)
Write
(B -Ba nk )
Row Active
( D- Ba nk )
Write
(D -B an k)
Row Active
( C- Ba nk )
Write
(C-Ban k)
Pr echarge
(All Banks)
: Don't care
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 3.0
34/45