M12L64164A_07 Datasheet, PDF (40/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
CLOCK
CKE
CS
1
2
3
4
5
tSS
*Note1
*Note3
6
7
8
*Note2
tSS
9 10 11 12 13 14 15 16 17 18 19
tSS
RAS
CAS
ADDR
Ra
Ca
A13
A12
A10/AP
DQ
Ra
Qa0
tSHZ
Qa1 Qa2
WE
DQM
Precharge
Power-Down
Entry
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Active
Power-down
Exit
Precharge
: Don't care
*Note: 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 3.0
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