M12L64164A_07 Datasheet, PDF (4/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
PARAMETER
SYMBOL
TEST CONDITION
Operating Current
(One Bank Active)
ICC1
Precharge Standby Current ^ICC2P
in power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
ICC2N
ICC2NS
Active Standby Current
in power-down mode
ICC3P
ICC3PS
Burst Length = 1, t RC ≥ t RC(min), I_OL = 0 mA,
tcc = tcc(min)
CKE ≤ VIL(max), tcc = tcc(min)
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≤ VIH(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
CKE ≤ VIL(max), tcc = tcc(min)
CKE & CLK ≤ VIL(max), tcc = ∞
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
ICC3N
ICC3NS
ICC4
ICC5
ICC6
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
IOL = 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
tRC ≥ tRC(min), tCC = tcc(min)
CKE ≤ 0.2V
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
VERSION
-5 -6 -7
UNIT NOTE
100 85 85 mA
1,2
2
mA
1
20
mA
10
10
mA
10
30
mA
25
mA
180 150 140 mA
1,2
180 150 140 mA
1
mA
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 3.0
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