M12L128324A_09 Datasheet, PDF (6/46 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V ，T_A = 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L128324A
Unit
V
V
ns
V
Output
870 _Ω
3.3V
1200 _Ω
VOH (DC) =2.4V , IOH = -2 mA
30pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50 _Ω
Vtt = 1.4V
50 _Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
Row cycle time
@ Auto Refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tRRD (min)
tRCD (min)
tRP (min)
tRAS (min)
tRAS (max)
tRC (min)
tRFC (min)
tCDL (min)
tRDL (min)
tBDL (min)
Version
-6
-7
12
14
18
18
18
20
42
42
100
60
63
60
63
1
2
1
Unit
Note
ns
1
ns
1
ns
1
ns
1
us
1
ns
1, 5
CLK
2
CLK
2
CLK
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.4
6/46