M12L128324A_09 Datasheet, PDF (5/46 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
ICC1
Precharge Standby Current ^ICC2P
in power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
ICC2N
ICC2NS
Active Standby Current
in power-down mode
ICC3P
ICC3PS
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
ICC3NS
Burst Length = 1
tRC ≥ tRC(min)
IOL = 0 mA
CKE ≤ VIL(max), t_CC = 10ns
CKE & CLK ≤ VIL(max), t_CC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), t_CC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), t_CC = ∞
input signals are stable
CKE ≤ VIL(max), t_CC = 10ns
CKE & CLK ≤ VIL(max), t_CC = ∞
CKE ≥ V_IH(min), CS ≥ V_IH(min), t_CC=15ns
Input signals are changed one time during 2clks
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), CLK ≤ VIL(max), t_CC = ∞
input signals are stable
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
I_OL = 0 mA
ICC4
Page Burst
2 Banks activated
t_CC = t_CC(min)
ICC5
tRFC ≥ tRFC(min)
ICC6
CKE ≤ 0.2V
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Version
-6
-7
120 ₁₀₀
2
1
25
9
7
6
30
15
270 240
270 240
2
Unit Note
mA 1,2
mA
mA
mA
mA
mA
mA 1,2
mA
mA
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.4
5/46