M12L128324A_09 Datasheet, PDF (22/46 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
8. Burst Stop & Interrupted by Precharge
CLK
1)Write Burst Stop (BL=8)
CMD
WR
STOP
DQM
DQ
D0 D1 D2 D3 D4 D5
tBDL ^*Note2
M12L128324A
CLK
1)Write interrupted by precharge (BL=4)
CMD
WR
DQM
tRDL
PRE
*Note1
DQ
D0 D1 D2 Mask
CLK
2)Read Burst Stop (BL=4)
CMD
RD
DQ(CL2)
STOP
*Note3
Q0 Q1
DQ(CL3)
Q0 Q1
CLK
2)Read interrupted by precharge (BL=4)
CMD
RD
PRE ^*Note3
DQ(CL2)
DQ(CL3)
Q0 Q1
Q0 Q1
9. MRS
1)Mod e Reg ister Set
CLK
CMD
*Note4
PRE
tRP
MRS
ACT
2CLK
*Note: 1. tRDL: 2 CLK; Last data in to Row Precharge.
2. tBDL: 1 CLK; Last data in to burst stop delay.
3. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
4. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.4
22/46