M12L2561616A-2S Datasheet, PDF (5/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L2561616A (2S)
Unit
V
V
ns
V
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-5
Row active to row active delay
t_RRD(min)
10
RAS to CAS delay
t_RCD(min)
15
Row precharge time
t_RP(min)
15
Row active time
t_RAS(min)
40
t_RAS(max)
@ Operating
t_RC(min)
55
Row cycle time
@ Auto refresh ^tRFC^(min)
55
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Refresh period (8,192 rows)
t_CDL(min)
t_RDL(min)
t_BDL(min)
t_CCD(min)
t_REF(max)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
Version
-6
12
18
18
42
100
60
60
1
3
1
1
64
2
1
Unit
Note
-7
14
ns
1
20
ns
1
20
ns
1
45
ns
1
us
63
ns
1
63
ns
1,5
CLK
2
CLK
2
CLK
2
CLK
3
ms
6
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t_RFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8 μ s.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.2
5/44