M12L2561616A-2S Datasheet, PDF (24/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
M12L2561616A (2S)
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS RAS CAS ^WE BA
ADDR
ACTION
HXXX
X
X
NOP
L HHH
X
X
NOP
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L
L
HH
BA
RA
Row (&Bank) Active ; Latch RA
L
L
H
L
BA
A10/AP NOP
L
L
L
H
X
X
Auto Refresh or Self Refresh
L
L
L
L OP code OP code Mode Register Access
HXXX
X
X
NOP
L HHH
X
X
NOP
L HH L
X
X
ILLEGAL
LHLH
BA CA, A10/AP Begin Read ; latch CA ; determine AP
LHL L
BA CA, A10/AP Begin Write ; latch CA ; determine AP
L
L
HH
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP Precharge
L
L
L
X
X
X
ILLEGAL
HXXX
X
X
NOP (Continue Burst to End Æ Row Active)
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
Term burst Æ Row active
LHLH
BA CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA CA, A10/AP Term burst, New Write, Determine AP
L
L
HH
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP Term burst, Precharge timing for Reads
L
L
L
X
X
X
ILLEGAL
HXXX
X
X
NOP (Continue Burst to End Æ Row Active)
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
Term burst Æ Row active
LHLH
BA CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA CA, A10/AP Term burst, New Write, Determine AP
L
L
HH
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP Term burst, Precharge timing for Writes
L
L
L
X
X
X
ILLEGAL
HXXX
X
X
NOP (Continue Burst to End Æ Row Active)
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L
L
HX
BA
RA, RA10 ILLEGAL
L
L
L
X
X
X
ILLEGAL
HXXX
X
X
NOP (Continue Burst to End Æ Row Active)
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L
L
HX
BA
RA, RA10 ILLEGAL
L
L
L
X
X
X
ILLEGAL
Note
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.2
24/44