M12L64164A_0712 Datasheet, PDF (37/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
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CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A13
A12
A10/AP
Ra
DQ
WE
DQM
Row Active Read
Qa0 Qa1
Qa2
Qa3
tSHZ
Clock
Supension
Read
Qb0
Qb1
tSHZ
Dc0
Dc2
*Note1
Read DQM
Write
DQM
Write
Clock
Suspension
Write
DQM
:Don't Care
*Note : 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2
37/45