M12L64164A_0712 Datasheet, PDF (36/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18 19
CKE
HIGH
CS
RAS
CAS
ADDR
Ra
Rb Ca
Cb
A13
A12
A10/AP
Ra
CL =2
DQ
CL =3
Rb
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
WE
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Row Active
( D - Bank )
Auto Precharge
Start Point
Write with
Auto Precharge
(D- Ban k)
Auto Precharge
Start Point
(D-Bank)
:Don't Care
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2
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