M12L64164A_0712 Datasheet, PDF (35/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
A13
CAa
RDb
CDb RBc
CBc
A12
A10/AP
CL =2
DQ
CL =3
RAa
RBb
QAa0 QAa1 QAa2 QAa3
RAc
t *Note1
CDL
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1 QBc2
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
:Don't Care
*Note : 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2
35/45