M12L64164A_09 Datasheet, PDF (31/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Page Read & Write Cycle at Same Bank @ Burst Length = 4
M12L64164A
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CS
RAS
CAS
tRCD
*Note2
ADDR
Ra
Ca
Cb
Cc
Cd
BA1
A10/AP
Ra
CL =2
DQ
CL =3
WE
DQM
Row Active
( A - Bank )
Qa0 Qa1 Qb0 Qb1 Qb2
Qa0 Qa1 Qb0 Qb1
tRDL
Dc0 Dc1 Dd0 Dd1
Dc0 Dc1 Dd0 Dd1
tCDL
Read
( A - Bank )
Read
( A - Bank )
*Note1
*Note3
W rite
( A - Bank )
W rite
( A - Bank )
Precharge
(A - Bank)
:Don't Care
Note: 1. To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid
bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 3.4
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