M12L128168A-2N Datasheet, PDF (3/46 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
M12L128168A (2N)
Automotive Grade
BALL CONFIGURATION (TOP VIEW)
(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
PIN DESCRIPTION
PIN
NAME
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A11
Address
BA0 , BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
DQ0 ~ DQ15
V_DD / V_SS
V_DDQ / V_SSQ
NC
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t_SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
3/46