M12L128168A-2N Datasheet, PDF (1/46 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
SDRAM
FEATURES
y JEDEC standard 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y Burst Read single write operation
y DQM for masking
y Auto & self refresh
(self refresh is not supported for VA grade)
y Refresh
- 64ms refresh period (4K cycle) for V grade
- 16ms refresh period (4K cycle) for VA grade
M12L128168A (2N)
Automotive Grade
2M x 16 Bit x 4 Banks
Synchronous DRAM
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 2,097,152 words
by 16 bits. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies
allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
ORDERING INFORMATION
Product ID
Max Freq.
Automotive range (V): -40℃ to +85℃
M12L128168A-5TVG2N
200MHz
M12L128168A-5BVG2N
200MHz
M12L128168A-6TVG2N
166MHz
M12L128168A-6BVG2N
166MHz
M12L128168A-7TVG2N
143MHz
M12L128168A-7BVG2N
143MHz
Automotive range (VA): -40℃ to +105℃
M12L128168A-5TVAG2N
M12L128168A-5BVAG2N
M12L128168A-6TVAG2N
M12L128168A-6BVAG2N
M12L128168A-7TVAG2N
M12L128168A-7BVAG2N
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
Package
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
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