M12L128168A-2N Datasheet, PDF (11/46 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V_IL and V_IH. During operation with
CKE high all inputs are assumed to be in valid state (low
or high) for the duration of setup and hold time around
positive edge of the clock for proper functionality and I_CC
specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All
other inputs are ignored from the next clock cycle after
CKE goes low. When all banks are in the idle state and
CKE goes low synchronously with clock, the SDRAM
enters the power down mode from the next clock cycle.
The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power
down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + t_SS”
before the high going edge of the clock, then the SDRAM
becomes active from the same clock edge accepting all
the input commands.
BANK ADDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
2,097,152 words x 16 bits memory arrays. The BA0~BA1
inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The
banks addressed BA0~BA1 are latched at bank active,
read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 21 address bits are required to decode the 2,097,152
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with
RAS and BA0~BA1 during bank active command. The 9
bit column addresses are latched along with CAS , WE
and BA0~BA1 during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high , The SDRAM
performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations
which require more than single clock cycle like bank
activate, burst read, auto refresh, etc. The device deselect
is also a NOP and is entered by asserting CS high. CS
high disables the command decoder so that RAS , CAS ,
WE and all the address inputs are ignored.
Elite Semiconductor Memory Technology Inc.
M12L128168A (2N)
Automotive Grade
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the CAS
latency, burst type, burst length, test mode and various
vendor specific options to make SDRAM useful for variety
of different applications. The default value of the mode
register is not defined, therefore the mode register must
be written after power up to operate the SDRAM. The
mode register is written by asserting low on CS , RAS ,
CAS and WE (The SDRAM should be in active mode
with CKE already high prior to writing the mode register).
The state of address pins A0~A11 and BA0~BA1 in the
same cycle as CS , RAS , CAS and WE going low is
the data written in the mode register. Two clock cycles is
required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation
as long as all banks are in the idle state. The mode
register is divided into various fields into depending on
functionality. The burst length field uses A0~A2, burst type
uses A3, CAS latency (read latency from column address)
use A4~A6, vendor specific options or test mode use
A7~A8, A10/AP~A11 and BA0~BA1. The write burst length
is programmed using A9. A7~A8, A10/AP~A11 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for various
burst length, burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and CS
with desired row and bank address, a row access is
initiated. The read or write operation can occur after a time
delay of t_RCD(min) from the time of bank activation. t_RCD is
the internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate
and read or write command should be calculated by
dividing t_RCD(min) with cycle time of the clock and then
rounding of the result to the next higher integer. The
SDRAM has four internal banks in the same chip and
shares part of the internal circuitry to reduce chip area,
Publication Date: Jun. 2012
Revision: 1.1
11/46