M12L16161A_08 Datasheet, PDF (28/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12L16161A
Revision History
Revision
0.1
0.2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Date
1998.10.23
1998.12.04
1999.12.10
2000.01.26
2000.04.25
2000.11.27
2001.02.22
2001.06.04
2001.09.07
2002.03.20
2003.12.16
2004.03.05
2005.05.10
2005.07.07
2005.10.06
2005.11.15
2007.05.03
2007.06.11
2007.07.20
2008.09.10
Description
Original
Add 200MHZ
1. Delete Preliminary
2. Rename the filename
Add –5.5 Spec
Correct error typing of C1 dimension
1. P5 Number of valid output data CAS Latency 3Æ 2ea
2. P17. P19. P21 Read Command shift right 1CLK
3. P15. P19. P20 Precharge Command shift left 1CLK
P6 modify tOH –6(2ns) & -7(2ns)
P3. P4 modify DC current
P5 modify AC parameters
1. P28 C1(Nom)=0.15mmÆ0.127mm
2. P28 delete symbol=ZD
Modify stand off=0.051~0.203mm
1. Correct typing error of timing (tRC; tRP;tRCD)
2. Add tRRD timing chart
Add “Pb-free” to ordering information
1. Modify I_CC1, I_CC2N, I_CC3N, I_CC4, I_CC5 spec
2. Delete –5.5, -6, -8, -10 AC spec
Add 60V FBGA
Modify VFBGA 60Ball Total high spec
Delete BGA ball name of packing dimensions
Modify Pin Configuration (TOP VIEW)
Modify tRAS(min) 40ns => 30ns and tRC(min) 55ns =>
48ns
Add Y spec. into TSOPII package dimension
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2008
Revision : 2.7
28/29