S1D13503F00A200 Datasheet, PDF (59/271 Pages) Epson Company – S1D13503 Graphics LCD Controller

Epson Research and Development
Vancouver Design Center
Page 51
Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1
Symbol
Parameter
Min
Typ
Max
t1
LP period
HT + HNDP - 10
t2
YD hold from LP falling edge
13t_OSC - 10
t3
LP pulse width
5t_OSC - 5
t6a
LP setup to XSCL falling edge
22t_OSC - 5
t6b
LP setup to XSCL2 falling edge
19.5t_OSC - 5
t7a
XSCL falling edge to LP falling edge
20t_OSC - 5
t7b
XSCL2 falling edge to LP falling edge
23.5t_OSC - 5
t8a
LP falling edge to XSCL falling edge
17t_OSC - 5
t8b
LP falling edge to XSCL2 falling edge
14.5t_OSC - 5
t9a
XSCL period
4t_OSC - 5
t9b
XSCL2 period
4t_OSC - 5
t10a
XSCL high width
t_OSC - 5
t10b
XSCL2 high width
t_OSC - 5
t11a
XSCL low width
3t_OSC - 10
t11b
XSCL2 low width
3t_OSC - 10
t12a
UD/LD setup to XSCL falling edge
1.5t_OSC - 10**
t12b
UD/LD setup to XSCL2 falling edge
1.5t_OSC - 10**
t13a
UD/LD hold from XSCL falling edge
t_OSC - 5
t13b
UD/LD hold from XSCL2 falling edge
t_OSC - 5
t14a
LP falling edge to XSCL rising edge
16t_OSC - 10
t14b
LP falling edge to XSCL2 rising edge
13.5t_OSC - 10
Where t_OSC = 1/f_OSC = input (pixel) clock period,
where HT = (number of horizontal panel pixels) * t_OSC,
where HNDP = horizontal non-display period in units of t_OSC (see Section 9.3 on page 84 for details).
** 5V operation, for 3.0V and 3.3V operation T12 will be 1.5t_OSC - 24.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hardware Functional Specification
Issue Date: 01/01/29
S1D13503
X18A-A-001-08