S1D13503F00A200 Datasheet, PDF (247/271 Pages) Epson Company – S1D13503 Graphics LCD Controller

Epson Research and Development
Vancouver Design Center
Page 9
3 8-BIT ISA BUS INTERFACE
For the purpose of the example shown below, the following conditions apply:
1. Indexed I/O with partial decoding, i.e. address lines A10 to A15 are not decoded for I/O cycles
Note
Partial decoding is quite safe on most ISA Bus systems as I/O addresses above 03FFh are rarely used.
2. I/O addresses are 0300h and 0301h (xxxxxx1100000000b and xxxxxx1100000001b)
3. 64Kbytes of display memory occupying $A segment
Note
The 74LS00 is simply used to detect the $B segment and invalidate the MEMCS# input.
Note
This memory configuration may conflict with a VGA card installed on the same bus, therefore either a
serial terminal or monochrome display adapter is recommended as the primary console.
This section provides the necessary settings to complete the interface between the S1D13503 and the 8-bit ISA Bus. Since
I/O addresses are partially decoded, there is no need to use a PAL for decoding.
8-Bit ISA Bus
AEN
REFRESH
SA0-19
SD0-7
SMEMW#
SMEMR#
IOW#
IOR#
IOCHRDY
1
SA16
4
5^B
62 ^A
3
74LS00
S1D13503
IOCS#
MEMCS#
BHE#
AB0-19
VD11-13,
VD15
VCC
10kΩ
DB0-7
MEMW
MEMR
IOW#
IOR#
READY
Figure 2: 8-Bit ISA Bus Implementation
ISA Bus Interface Considerations
Issue Date: 01/01/30
S1D13503
X18A-G-003-05