EN25F20 Datasheet, PDF(8/31 Page) Eon Silicon Solution Inc. – 2 Mbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F20 Datasheet, PDF (8/31 Pages) Eon Silicon Solution Inc. – 2 Mbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F20

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

Table 4. Instruction Set

Instruction Name

Write Enable

Write Disable / Exit

OTP mode

Read Status

Write Status

Read Data

Fast Read

Page Program

Sector Erase

Block Erase

Chip Erase

Deep Power-down

Release from Deep

Power-down, and

read Device ID

Release from Deep

Power-down

Manufacturer/

Device ID

Read Identification

Enter OTP mode

Byte 1

Code

06h

04h

Byte 2

05h

(S7-S0)(1)

01h

S7-S0

03h

A23-A16

0Bh

A23-A16

02h

A23-A16

20h

A23-A16

D8h/ 52h A23-A16

C7h/ 60h

B9h

dummy

ABh

90h

dummy

9Fh

(M7-M0)

3Ah

Byte 3

A15-A8

dummy

(ID15-ID8)

Byte 4 Byte 5 Byte 6

A7-A0

(D7-D0)

dummy

D7-D0

(Next byte)

(D7-D0)

(Next byte)

dummy (ID7-ID0)

00h(5) (M7-M0)

(ID7-ID0)

n-Bytes

continuous

(2)

continuous

(Next Byte)

continuous

(4)

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis â( )â indicate data being read from

the device on the DO pin.

2. The Status Register contents will repeat continuously until CS# terminate the instruction.

3. All sectors may use any address within the sector.

4. The Device ID will repeat continuously until CS# terminate the instruction.

5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.

00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.

Table 5. Manufacturer and Device Identification

OP Code (M7-M0)

(ID15-ID0)

(ID7-ID0)

ABh

11h

90h

1Ch

11h

9Fh

1Ch

3112h

Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable

Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip

Erase (CE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction

code, and then driving Chip Select (CS#) High.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2007/05/15

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