EN25F20 Datasheet, PDF(4/31 Page) Eon Silicon Solution Inc. – 2 Mbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F20 Datasheet, PDF (4/31 Pages) Eon Silicon Solution Inc. – 2 Mbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F20

MEMORY ORGANIZATION

The memory is organized as:

z 262,144 bytes

z Uniform Sector Architecture

4 blocks of 64-Kbyte

64 sectors of 4-Kbyte

z 1024 pages (256 bytes each)

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,

Block or Chip Erasable but not Page Erasable.

Table 2. Uniform Block Sector Architecture

Block

Sector

Address range

03F000h

03FFFFh

030000h

02F000h

030FFFh

02FFFFh

020000h

01F000h

020FFFh

01FFFFh

010000h

00F000h

010FFFh

00FFFFh

004000h

003000h

002000h

001000h

000000h

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

OPERATING FEATURES

SPI Modes

The EN25F20 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0

(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure

3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK

signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.

Data output on the DO pin is clocked out on the falling edge of SCK.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2007/05/15

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