EN29LV160A Datasheet, PDF (18/43 Pages) Eon Silicon Solution Inc. – 16 MEGABIT (2048K X 8- BIT / 1024 K X 16-BIT) FLASH MEMORY

EN29LV160A
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence. DQ2 toggles when the system reads at addresses within those sectors that have been
selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is
toggling. Typically, a system would note and store the value of the toggle bit after the first read. After
the second read, the system would compare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling,
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Operation
Standar
d Mode
Erase
Suspend
Mode
Embedded Program
Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend Program
DQ7
DQ7#
0
1
Data
DQ7#
DQ6
Toggle
Toggle
No
Toggle
Data
Toggle
DQ5
0
0
0
Data
0
DQ3
N/A
1
N/A
Data
N/A
DQ2
No
toggle
Toggle
RY/BY
#
0
0
Toggle
1
Data
1
N/A
0
This Data Sheet may be revised by subsequent versions ₁₈ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2005/01/07