EN25T16A Datasheet, PDF (15/35 Pages) Eon Silicon Solution Inc. – 16 Megabit Uniform Sector, Serial Flash Memory

EN25T16A
Figure 9. Read Data Instruction Sequence Diagram
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 10 and Figure 10.1 for SPI mode and SP2 mode. The first
byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The whole memory can, therefore, be read with a single
Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Notes : The number of dummy cycles in SPI and SP2 mode are eight and four.
This Data Sheet may be revised by subsequent versions
15
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2011/04/15
www.eonssi.com