EN25T16A Datasheet, PDF (13/35 Pages) Eon Silicon Solution Inc. – 16 Megabit Uniform Sector, Serial Flash Memory

Table 6. Status Register Bit Locations
EN25T16A
S7
S6
S5
S4
S3
S2
S1
S0
SRP OTP_LOCK
Status Register
bit
Protect
(note 1)
BP2
BP1
BP0
WEL
WIP
(Block Protected (Block Protected (Block Protected (Write Enable (Write In
bits)
bits)
bits)
Latch)
Progress bit)
1 = status
register write
disable
1 = OTP
sector is
protected
Non-volatile bit
Mode 1
Mode 0
(note 2)
(note 2)
(note 2)
Non-volatile bit Non-volatile bit Non-volatile bit
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of
the area to be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0)
bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page
Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase
(CE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
Mode1, Mode0 bits. Default value is SPI mode (00), user can change this value by change mode
commands to change the interface mode. This device also support SP2 mode (01).
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal
allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit
is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status
Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
This Data Sheet may be revised by subsequent versions
13
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2011/04/15
www.eonssi.com