EN25Q40_11 Datasheet, PDF (15/49 Pages) Eon Silicon Solution Inc. – 4 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q40
Figure 8.1 Read Status Register Instruction Sequence under EQIO Mode
Table 6. Status Register Bit Locations
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Status
Register
Protect
1 = status
register
write
disable
OTP_LOCK
bit
(note 1)
1 = OTP
sector is
protected
WPDIS
(WP# disable)
BP2
BP1
BP0
WEL
WIP
(Block Protected (Block Protected (Block Protected (Write Enable (Write In
bits)
bits)
bits)
Latch)
Progress bit)
1 = WP#
disable
0 = WP#
enable
Reserved
bits
(note 2)
(note 2)
(note 2)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
Non-volatile bit
Non-volatile bit
Non-volatile bit Non-volatile bit Non-volatile bit volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of
the area to be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0)
bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page
Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2, BP1,
This Data Sheet may be revised by subsequent versions
15
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. F, Issue Date: 2011/11/02
www.eonssi.com