EN29LV160B Datasheet, PDF (13/43 Pages) Eon Silicon Solution Inc. – 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory

Hardware Data protection
EN29LV160B
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low V_CC Write Inhibit
When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
V_LKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH, or WE# = V_IH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = V_IL, WE#= V_IL and OE# = V_IH, the device will not accept commands on the rising edge of WE#.
This Data Sheet may be revised by subsequent versions
13
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
Rev. I, Issue Date: 2011/10/26
www.eonssi.com