EP5352Q Datasheet, PDF (8/16 Pages) Enpirion, Inc. – 500/600/800mA Synchronous Buck Regulators With Integrated Inductor

Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
EP5382Q/EP5362Q/EP5352Q
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA. The ENABLE pin must
not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Application Information
Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP53x2Q family
uses a 3 pin VID, or Voltage ID, output voltage
select arrangement. This allows the designer
to choose one of seven preset voltages, or to
use an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to V_IN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to V_IN or GND or alternatively can be
driven by standard logic levels. Logic low is
defined as V_LOW ≤ 0.4V. Logic high is defined
as V_HIGH ≥ 1.4V. Any level between these two
values is indeterminate. These pins must not
be left floating.
Table 1. Voltage select settings.
VS2
VS1
VS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
V_OUT
3.3
2.5
2.8
1.2
3.0
1.8
2.7
External
External Voltage Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to V_IN or logic “high”.
The EP53x2Q uses a separate feedback pin,
V_FB, when using the external divider. VSENSE
must be connected to V_OUT as indicated in
Figure 5.
©Enpirion 2009 all rights reserved, E&OE
03132
8
4/28/2009
www.enpirion.com
Rev:B