EP5352Q Datasheet, PDF (10/16 Pages) Enpirion, Inc. – 500/600/800mA Synchronous Buck Regulators With Integrated Inductor

EP5382Q/EP5362Q/EP5352Q
LAYOUT CONSIDERATIONS*
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success
Recommendation 1: Input and output filter capacitors should be placed as close to the EP53x2QI
package as possible to reduce EMI from input and output loop AC currents. This reduces the
physical area of the Input and Output AC current loops.
Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the
Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground
pad for the input and output filter capacitors should be isolated ground islands and should be
connected to system ground as indicated in recommendation 3 and recommendation 5.
Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect
ground terminals of the Input capacitor and the output capacitor to the system ground plane. This
provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and
suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7).
Recommendation 4: The large thermal pad underneath the component must be connected to the
system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill
size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for
heat dissipation from the converter.
Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be
the first layer immediately below the surface layer (PCB layer 2). This ground plane should be
continuous and un-interrupted below the converter and the input and output capacitors that carry
large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an
uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the
EN5312QI and its input and output capacitors. The vias that connect the input and output capacitor
grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as
well.
Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or
control lines underneath the converter package.
Figure 6 shows an example schematic for the EP53x2Q using the internal voltage select. In this
example, the device is set to a V_OUT of 1.2V (VS2=0, VS1=1, VS0=1).
©Enpirion 2009 all rights reserved, E&OE
03132
10
4/28/2009
www.enpirion.com
Rev:B