EP5352Q Datasheet, PDF (12/16 Pages) Enpirion, Inc. – 500/600/800mA Synchronous Buck Regulators With Integrated Inductor

Thermal Vias to Ground Plane
EP5382Q/EP5362Q/EP5352Q
Package
Outline
C_IN
C_OUT
Vias to Ground Plane
Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter
capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
Enpirion has developed a break-through in package technology that utilizes the lead frame as part of
the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced
electrical lead resistance, and in overall foot print. However, it does require some special
considerations.
As part of the package assembly process, lead frame construction requires that for mechanical
support, some of the lead-frame metal be exposed at the point where wire-bond or internal passives
are attached. This results in several small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EP53x2QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 9 represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer of the PCB.
NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the
perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC
MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.
©Enpirion 2009 all rights reserved, E&OE
03132
12
4/28/2009
www.enpirion.com
Rev:B