EV1340QI Datasheet, PDF (3/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

PIN
43
44
45
46
47
48
49-52
55
EV1340QI
NAME
EAOUT
VREF
VSENSE
EN_PB
FQADJ
VDDQOK
NC(SW)
Thermal
Pad
(PGND)
FUNCTION
Optional Error Amplifier Output. Allows for customization of the control loop.
External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid-
point of the resistor divider is connected to VREF. The resistor divider has to be chosen to
make the voltage applied to this pin 600mV. An optional capacitor (for soft-start) may be
connected from VREF to AGND.
This pin senses the output voltage when the device is in pre-bias (or backfeed) mode.
Connect to VOUT if EN_PB is high. Leave this pin floating if EN_PB is pulled to GND.
Monotonic start-up with pre-bias is enabled by either pulling this pin high or letting it float. A
logical low on this pin will disable pre-bias mode operation.
Optimized frequency adjust pin. Connect a 3.57kΩ resistor from this pin to AGND to optimize
on switching frequency.
This is an active high input pin that indicates the externally supplied VDDQ input has reached
its POK level. This pin should be tied to the VDDQ regulator POK output. It has an internal
pull-up, and can be left floating if not needed.
No Connect – these pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow these guidelines may result in damage to the device.
Not a perimeter pin. Device thermal pad and PGND. Connected to the system ground plane.
See Layout Recommendations section.
©Enpirion 2011 all rights reserved, E&OE
06218
3
10/19/2011
www.enpirion.com
Rev: A