EV1340QI Datasheet, PDF (15/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

Output Capacitor Selection
The EV1340 has been optimized for use with
200µF of output capacitance. Low ESR
ceramic capacitors are required with X5R or
X7R dielectric formulation. Y5V or equivalent
dielectric formulations must not be used as
these lose capacitance with frequency,
temperature and bias voltage. The capacitors
shown in the table below are some typical
output capacitors. Other capacitors with similar
characteristics may also be used.
Typical Recommended Output Capacitors
Description
47µF, 10V,
X5R, 1206
47µF, 6.3V,
X5R, 1206
100µF, 6.3V,
X5R, 1206
MFG
Taiyo
Yuden
Taiyo
Yuden
Murata
Murata
P/N
LMK316BJ476ML-T
JMK316BJ476ML-T
GRM31CR60J476ME19L
GRM31CR60J107M
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 1.5MHz switching frequency output
impedance, denoted as Z, is comprised mainly
of effective series resistance, ESR, and
effective series inductance, ESL:
Z = ESR + ESL
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
1 ₌ 1 ₊ 1 _{+ ... +} 1
Z _Total Z₁ Z ₂
Z_n
Typical Ripple Voltages
Output Capacitor
Configuration
2 x 100 µF
Typical Output Ripple (mVp-p)
VDDQ = 1.5V, V_OUT = 0.75V
<10mV
EV1340QI
Schottky Diode Selection
The EV1340 requires a Schottky diode from
the SW pin to the VDDQ pin. The anode
should be facing the SW pin and the cathode
facing the VDDQ pin. Enpirion has
characterized the ST Microelectronics
TMBYV10-40FILM diode with the EV1340.
Contact Enpirion Applications Support for
alternate options for this diode.
Low V_IN Applications
The EV1340 is an excellent solution for low V_IN
applications where highest efficiency is very
critical. Reference the low V_IN efficiency chart
in the Typical Performance Characteristics
section for estimated efficiencies at several use
cases. In these applications, a precision
voltage reference is required for the VREF
input of the EV1340. Figure 7 shows a
schematic for a typical low V_IN application.
Figure 7: Typical Low V_IN Application Schematic
Power-Up Sequencing
During power up, neither ENABLE nor VDDQ
should be asserted before AVIN. There are two
common acceptable turn-on/off sequences for
the device. ENABLE can be tied to AVIN and
come up with it, and VDDQ can be ramped up
and down as needed. Alternatively, VDDQ can
be brought high after AVIN is asserted, and the
device can be turned on and off by toggling the
ENABLE pin.
©Enpirion 2011 all rights reserved, E&OE
06218
15
10/19/2011
www.enpirion.com
Rev: A