EV1340QI Datasheet, PDF (16/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

Layout Recommendations
Figure 8 and Figure 9 shows critical
components along with top and bottom traces
of a recommended minimum footprint of the
EV1340QI layout with ENABLE tied to V_IN.
Alternate ENABLE configurations and other
small signal pins need to be connected and
routed according to specific customer
application. Please see the Gerber files on the
Enpirion website www.enpirion.com for exact
dimensions and other layers. Please refer to
Figures 8 and 9 while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EV1340QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EV1340QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: There are a total of
seven PGND pins dedicated to the input and
output circuits. The input and output ground
currents should be separated with a slit until
they reach the seven PGND pins to help
minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Enpirion
website www.enpirion.com.
Recommendation 4: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible.
EV1340QI
Figure 8: Top PCB Layer with Critical
Components and Copper for
Minimum Footprint (Top View)
Figure 9: Bottom PCB Layer with Critical
Components and Copper for
Minimum Footprint (Top View)
©Enpirion 2011 all rights reserved, E&OE
06218
16
10/19/2011
www.enpirion.com
Rev: A