EV1340QI Datasheet, PDF(17/20 Page) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

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EV1340QI Datasheet, PDF (17/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

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The drill diameter of the vias should be

0.33mm, and the vias must have at least 1 oz.

copper plating on the inside wall, making the

finished hole size around 0.20-0.26mm. Do not

use thermal reliefs or spokes to connect the

vias to the ground plane. This connection

provides the path for heat dissipation from the

converter. Please see Figures 8, 9, 10, and 11.

Recommendation 5: Multiple small vias (the

same size as the thermal vias discussed in

recommendation 4 should be used to connect

ground terminal of the input capacitor and

output capacitors to the system ground plane.

It is preferred to put these vias under the

capacitors along the edge of the GND copper

closest to the +V copper. Please see Figure 8

and Figure 9. These vias connect the

input/output filter capacitors to the GND plane

and help reduce parasitic inductances in the

input and output current loops. If the vias

cannot be placed under CIN and COUT, then put

them just outside the capacitors along the GND

slit separating the two components. Do not use

thermal reliefs or spokes to connect these vias

to the ground plane.

Recommendation 6: AVIN1 and AVIN2 are

the power supplies for the internal small-signal

control circuits. AVIN1 and AVIN2 should be

the filter capacitor CAVIN is connected closely

from the AVIN1 and AVIN2 pins to AGND for

proper filtering of the control circuit.

Recommendation 7: The layer 1 metal under

the device must not be more than shown in

Figure 8. See the section regarding exposed

metal on bottom of package. As with any

switch-mode DC/DC converter, try not to run

sensitive signal or control lines underneath the

converter package on other layers.

Recommendation 8: The VOUT sense trace to

RA should come just after the last output filter

capacitor COUT2. Keep the sense trace as

EV1340QI

short as possible in order to avoid noise

coupling into the control loop.

Recommendation 9: Keep RA, CA, R1 and RB

close to the VFB pin (see Figure 8). The VFB

pin is a high-impedance, sensitive node. Keep

the trace to this pin as short as possible.

Whenever possible, connect RB directly to the

AGND pin instead of going through the GND

plane.

Recommendation 10: Connect AGND to the

ground plane through a single via as close to

the AGND pin as possible. This establishes the

connection between AGND and PGND.

Recommendation 11: The VREF pin sets the

reference voltage for VOUT and should be as

clean as possible. The connection from VDDQ

to VREF should begin from the CIN input

capacitor to VREF through a resistor voltage

divider (RC, RD). The soft-start capacitor CSS,

RC, and RD form a low-pass RC filter for the

VREF pin. A bypass capacitor C1 should be

placed close to the RC resistor for additional

filtering. The long trace from VDDQ to C1

forms a low-pass LC filter with C1 and helps

further reduce noise coupling to VREF.

Recommendation 12: The Schottky diode D1

should be connected with anode to SW and

cathode to VDDQ with very low inductance

traces. Place D1 directly under the device as

shown in Figure 9. Vias near SW and VDDQ

connect these pins to the D1 terminals. The

recommended diode for this layout is ST

Microelectronics TMBYV10-40FILM. Contact

Enpirion Applications Support for alternate

options for this diode.

Recommendation 13: Enpirion provides

schematic and layout reviews for all customer

designs. It is highly recommended for all

customers to take advantage of this service.

Please send pdf schematic files and Gerber

layout files of the power section to your local

sales contact or to Enpirion Applications

Support.

06218

10/19/2011

www.enpirion.com

Rev: A

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