EN2390QI Datasheet, PDF(11/21 Page) Enpirion, Inc. – 9A Voltage Mode Synchronous Buck PWM

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EN2390QI Datasheet, PDF (11/21 Pages) Enpirion, Inc. – 9A Voltage Mode Synchronous Buck PWM

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Power Up Sequence

The EN2390QI is designed to be powered by either

a single input supply (PVIN) or two separate

supplies: one for PVIN and the other for AVIN.

Single Input Supply Application (PVIN):

The EN2390QI has an internal linear regulator that

converts PVIN to 3.3V. The output of the linear

regulator is provided on the AVINO pin. AVINO

should be connected to AVIN on the EN2390QI. In

this application, the following external components

are required: Place a 1ÂµF, X5R, capacitor between

AVINO and AGND as close as possible to AVINO.

Place a 0.1ÂµF, X5R, capacitor between AVIN and

AGND as close as possible to AVIN. In addition,

place a resistor (RVB) between VDDB and AVIN, as

shown in Figure 1. Enpirion recommends

RVB=4.75kâ¦. In this application, ENABLE cannot be

asserted before PVIN. If no external enable signal

is used, tying ENABLE to AVIN meets this

requirement.

Dual Input Supply Application (PVIN and AVIN):

In this application, place a 0.1ÂµF, X5R, capacitor

between AVIN and AGND as close as possible to

AVIN. Refer to Figure 5 for a recommended

schematic for a dual input supply application.

For dual input supply applications, the sequencing

of the two input supplies, PVIN and AVIN, is very

important. During power up, neither ENABLE nor

PVIN should be asserted before AVIN. There are

two common acceptable turn-on/off sequences for

the device. ENABLE can be tied to AVIN and come

up with it, and PVIN can be ramped up and down

as needed. Alternatively, PVIN can be brought high

after AVIN is asserted, and the device can be

turned on and off by toggling the ENABLE pin.

Enable Operation

The ENABLE pin provides a means to enable

normal operation or to shut down the device. A

logic high will enable the converter into normal

operation. When the ENABLE pin is asserted (high)

the device will undergo a normal soft-start. A logic

low will disable the converter. A logic low will power

down the device in a controlled manner and the

device is subsequently shut down. The ENABLE

signal has to be low for at least the ENABLE

Lockout Time (8ms) in order for the device to be re-

enabled.

Pre-Bias Operation

The EN2390QI is not designed to be turned on into

a pre-biased output voltage.

EN2390QI

Figure 5: Dual Input Supply (PVIN and AVIN)

Recommended Schematic

Frequency Synchronization

The switching frequency of the EN2390QI can be

phase-locked to an external clock source to move

unwanted beat frequencies out of band. The

internal switching clock of the EN2390QI can be

phase locked to a clock signal applied to the S_IN

pin. An activity detector recognizes the presence of

an external clock signal and automatically phase-

locks the internal oscillator to this external clock.

Phase-lock will occur as long as the input clock

frequency is in the range of 0.8MHz to 1.6MHz.

When no clock is present, the device reverts to the

free running frequency of the internal oscillator.

Adding a resistor (RFS) to the FADJ pin will adjust

the frequency lower. If a 3Kâ¦ resistor is placed on

FADJ the nominal switching frequency of the

EN2390QI is 1MHz. The efficiency performance of

the EN2390QI for various PVIN/VOUT

combinations can be optimized by adjusting the

switching frequency. Table 1 shows recommended

RFS values for various PVIN/VOUT combinations in

order to optimize performance of the EN2390QI.

PVIN

12V

VOUT

TBD

RFS

TBD

Table 1: Recommended RFS Values

Enpirion Confidential

www.enpirion.com, Page 11

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