EMC646SP16J Datasheet, PDF (7/65 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM

Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 1 : PIN Descriptions
Symbol
Type
Descriptions
A[21:0]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
CLK
(Note1)
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
ADV#
(Note1)
Input
Address valid: Indiates that a valid address is present on the address inputs. Addresses can be latched on
the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during
asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations
access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby or deep power-down mode.
OE#
Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB#
Input Lower byte enable. DQ[7:0]
UB#
Input Upper byte enable. DQ[15:8]
DQ[15:0] Input/Output Data inputs/outputs.
WAIT
(Note1)
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#.
WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at
the end of a row unless wrapping within the burst length. WAIT is asserted and should be ignored during
asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH.
RFU
-
Reserved for future use.
Vcc
Supply Device power supply: (1.70V.1.95V) Power supply for device core operation.
VccQ
Supply I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
Vss
Supply Vss must be connected to ground.
VssQ
Supply VssQ must be connected to ground.
Note:
1. When using asynchronous mode or page mode exclusively, CLK and ADV# inputs can be tied to Vss. WAIT will be asserted but should be ignored during asynchronous
and page mode operations.
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