EMC646SP16J Datasheet, PDF (22/65 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM

Preliminary
EMC646SP16J
4Mx16 CellularRAM
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Fig-
ure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the
register access software sequence with DQ = 0001h on the third cycle.
Figure 16: Bus Configuration Register Definition
A[21:20] A[19:18] A[17:16] A15
A14 A13 A12 A11 A10
A9
A8
A7
A6 A5 A4
A3
A2 A1 A0
21-20
Reserved
19-18
Register
Select
17-16
Reserved
15
Operating
Mode
14
Initial
Latency
13 12 11
Latency
Counter
10
WAIT
Polarity
9
Reserved
8
WAIT
Configuration(WC)
7
Reserved
6
Reserved
54
Drive
Strength
3
Burst
Wrap(BW)*
210
Burst
Length(BL)*
All must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0”
BCR[14]
Initial Access Latency
0
Variable (default)
1
Fixed
BCR[13]
0
0
0
0
1
1
1
1
BCR[12]
0
0
1
1
0
0
1
1
BCR[11]
0
1
0
1
0
1
0
1
Latency Counter
Code 0 - Reserved
Code 1 - Reserved
Code 2
Code 3 (default)
Code 4
Code 5
Code 6
Code 7 - Reserved
BCR[10]
WAIT Polarity
0
Active LOW
1
Active HIGH (default)
BCR[15]
Operating Mode
0
Synchronous burst access mode
1
Asynchronous access mode (default)
BCR[19]
0
1
0
BCR[18]
0
0
1
Register Select
Select RCR
Select BCR
Select DIDR
Note: 1. Burst wrap and length apply to both READ and WRITE operations.
BCR[3]
0
1
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
BCR[5]
0
0
1
1
BCR[4]
0
1
0
1
Drive Strength
Full
1/2 (default)
1/4
Reserved
BCR[8]
0
1
WAIT Configuration
Asserted during delay
Asserted one data before delay(default)
BCR[2]
0
0
0
1
1
BCR[1]
0
1
1
0
1
Others
BCR[0] Burst Length (Note 1)
1
4 words
0
8 words
1
16 words
0
32 words
1
Continuous burst (default)
Reserved
22